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CY28517
PCI Express Clock Generator
Features

Selectable, Triangle, and Lexmark profiles SMbus support with readback capabilities 3.3V power supply Packages are Pb free and ROHS compliant 28-pin TSSOP packages 100M x4 25M x2 27M x1 48M x1
Four 100 MHz differential clocks 48 MHz clock Two 25 MHz clocks 27 MHz Reference Clock OE control per clock output Selectable drive strength per output
Logic Block Diagram
OE_100_25
X1/CLK X2
XTAL OSC
27M
100MT[A:D]
PLL1
RSET
100MC[A:D]
PLL2
48M
PLL3
25M[A:B]
SDATA SCLK
SMBus Logic
Cypress Semiconductor Corporation Document #: 001-42225 Rev. *A
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised November 02, 2007
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Pinouts
Figure 1. Pin Diagram - 28 Pin TSSOP
VDDX X1/ICLK X2 VSSX VDD25M 25MA 25MB OE_100_25 VSS25 100MC_C 100MT _C VSS100 100MC_D 100MT _D 1 2 3 4 5 28 27 26 25 24 27M SCLK SDAT A VSS48 48M VDD48 VDD100 VSS100 RSET 100MC_A 100MT _A VDD100 100MC_B 100MT _B
7 8 9 10 11 12 13 14
CY28517
6
23 22 21 20 19 18 17 16 15
Table 1. Pin Definitions - 28 Pin TSSOP Pin No. 1 2 3 4 5 6,7 8 9 VDDX X1/ICLK X2 VSSX VDD25 25M[A:B] OE_100_25 VSS25 Name I O, SE PWR PWR O, SE I, PD PWR Type PWR Description 3.3V Power Supply for XTAL and REF 27 MHz Crystal Input/ Clock Input 27 MHz Crystal Output Ground for XTAL and REF 3.3V Power Supply for 25 MHz Outputs 25 MHz Clock Input for Enabling/Disabling 25 MHz [A:B] and 100 MHz [A:D] Clock. It is a high true signal and has an internal pull down resistor with value >100 KOhms. Ground for 25 MHz Outputs
10, 11, 13, 14, 100MT/C[A:D] 15, 16, 18, 19 12, 21 17, 22 20 23 24 25 26 27 28 VSS100 VDD100 RSET VDD48 48M VSS25 SDATA SCLK 27M
O, DIF Differential 100 MHz Clocks Intel Type-X buffer. PWR PWR I PWR O, SE PWR IO I O, SE Ground for 100 MHz Outputs 3.3V Power Supply for 100 MHz Outputs A Precision resistor is attached to this pin, which is connected to the internal current reference 3.3V Power Supply for 48 MHz Outputs 48 MHz Clock Ground for 48 MHz Outputs SMBus Compatible SDATA SMBus Compatible SCLOCK Reference Clock. 3.3V 27 MHz clock output
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CY28517
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. This is a RAM based technology which does not keep its value when power is off or during a power transition.
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write or read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. The block write and block read protocol is outlined in Table 3 while Table 4 on page 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h) for write and 11010011(D3h) for read.
Table 2. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation, 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 Start Slave address - 7 bits Write Acknowledge from slave Description 1 2:8 9 10 Bit Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8-bit `00000000' stands for block operation Acknowledge from slave Repeat start Slave address - 7 bits Read Acknowledge from slave Byte count from slave - 8 bits Acknowledge Data byte from slave - 8 bits Acknowledge Data byte from slave - 8 bits Acknowledge Data bytes from slave/Acknowledge Data byte N from slave - 8 bits Not Acknowledge Stop Block Read Protocol Description
Command Code - 8-bit `00000000' stands for block 11:18 operation Acknowledge from slave Byte Count - 8 bits Acknowledge from slave Data byte 0 - 8 bits Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data Byte N/Slave Acknowledge... Data Byte N - 8 bits Acknowledge from slave Stop 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56
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Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write = 0 Acknowledge from slave Description 1 2:8 9 10 Bit Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits `1xxxxxxx' stands for byte operation, of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Data byte from slave - 8 bits Not Acknowledge Stop Byte Read Protocol Description
Command Code - 8 bits `1xxxxxxx' stands for byte 11:18 operation, bits[6:0] of bits[6:0] the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte from master - 8 bits Acknowledge from slave Stop 19 20 21:27 28 29 30:37 38 39
19 20:27 28 29
Control Registers
Byte 0:Control Register 0
Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 27M 48M 25M_B 25M_A 100M[T/C]D 100M[T/C]C 100M[T/C]B 100M[T/C]A Name 27M Output Enable 0 = Disable (Hi-Z), 1 = Enable 48M Output Enable 0 = Disable (Hi-Z), 1 = Enable 25M_B Output Enable 0 = Disable (Hi-Z), 1 = Enable 25M_A Output Enable 0 = Disable (Hi-Z), 1 = Enable 100M[T/C]D Output Enable 0 = Disable (Hi-Z), 1 = Enable 100M[T/C]C Output Enable 0 = Disable (Hi-Z), 1 = Enable 100M[T/C]B Output Enable 0 = Disable (Hi-Z), 1 = Enable 100M[T/C]A Output Enable 0 = Disable (Hi-Z), 1 = Enable Description
Byte 1: Control Register 1
Bit 7 6 5 4 3 @Pup 1 0 0 0 0 Name 100M_D_Drive Strength Reserved Reserved Reserved Reserved Description Choose 100M[A;D] RSET Multiplier 0 - 2X, 1 - 6X Reserved, Set = 0 Reserved, Set = 0 Reserved, Set = 0 Reserved, Set = 0
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Byte 1: Control Register 1 (continued)
Bit 2 1 @Pup 0 0 Name Spread Control
Bit2 0 0 1 1 Bit1 0 1 0 1 Spread Value -0.35 Triangular -0.50 Triangular -0.35 Lexmark -0.50 Lexmark
Description
0
0
100M Spread Enable
PLL1 Spread Spectrum Enable 0 = Spread off, 1 = Spread on
Byte 2: Control Register 2
Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description
Byte 3: Control Register 3
Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description
Byte 4: Control Register 4
Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 0 0 Reserved Reserved Reserved Reserved Reserved VCO Frequency Control Reserved Reserved Name Reserved Reserved Reserved Reserved Reserved Must set this bit to 0 after power up to ensure proper operation of the device Reserved Reserved Description
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Byte 5: Control Register 5
Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description
Byte 6: Vendor ID Register
Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 1 0 0 0 Name Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description
Crystal Recommendations
The CY28517 requires a Parallel Resonance Crystal. Substituting a series resonance crystal causes the CY28517 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300 ppm frequency shift between series and parallel crystals due to incorrect loading. Table 5. Crystal Recommendations Frequency (Fund) 27.00 MHz Cut Parallel Load Cap 18 pF Eff Series Rest 30 Ohm Drive (Max) 50 W Tolerance (Max) 30 ppm Stability (Max) 10 ppm Aging (Max) 5 ppm/Yr
Crystal Loading
Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance of the crystal must be considered to calculate the appropriate capacitive loading (CL). Figure 2 on page 7 shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It's a common misconception that load capacitors are in parallel with the crystal and must be approximately equal to the load capacitance of the crystal. This is not true.
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) must be calculated to provide equal capacitive loading on both sides.
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Figure 2. Crystal Loading Example
C lo c k C h ip
Output Enable
The Output Enable (OE_100_25) signal is active HIGH input used for clean stopping and starting the selected 100M and 25M outputs. To recognize as a valid assertion or deassertion, the signal is a debounced signal in that its state must remain unchanged during two consecutive rising edges of 25 MHz. The assertion and deassertion of this signal is absolutely asynchronous.
C i1
C i2 P in 3 to 6 p
C s1
X1
X2
C s2 T ra c e 2 .8 p F
Output Enable Deassertion
Upon deasserting the Output Enable pin (OE_100_25) all 100M/25M outputs are stopped after their next transition. The final state of all stopped 100M/25M signals is LOW.
XTAL Ce1
Ce2
T r im 33pF
Output Enable Assertion
All 100 MHz/25 MHz outputs that were stopped resumes normal operation in a glitch free manner. The maximum latency from the assertion to active outputs is between 2-6 clock periods of 100 MHz/25 MHz with all 100M/25M outputs resuming simultaneously. Table 6. Output Enable Table Output Enable 0 1 27M On On 48M On On 25M[A:B] 100MT/C[A:D] Low On Hi-Z On
Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Ce = 2 * CL - (Cs + Ci) Total Capacitance (as seen by the crystal) CLe
=
1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2
)
CL ................................................... Crystal load capacitance CLe ......................................... Actual loading seen by crystal using standard value trim capacitors Ce ..................................................... External trim capacitors Cs ..............................................Stray capacitance (terraced) Ci .......................................................... Internal capacitance
Absolute Maximum Conditions
Parameter
VDD VIN TS TA TJ TSOL ESDHBM UL-94 MSL Supply Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction Pb free Soldering Process Temperature ESD Protection (Human Body Model) Flammability Rating Moisture Sensitivity Level MIL-STD-883, Method 3015 At 1/8 in. Relative to VSS Non-functional Functional Functional
Description
Condition
Min
-0.5 -0.5 -65 5 - - 2000
Max
4.6 VDD + 0.5 150 65 150 260 - V-0 1
Unit
V VDC C C C C V
Multiple Supplies: The voltage on any input or IO pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.
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DC Electrical Specifications
Parameter
VDD VILI2C VIHI2C VIL VIH IIL IIH VOL VOH IOZ CIN COUT LIN VXIH VXIL IDD3.3V IPD3.3V
Description
3.3V Operating Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Leakage Current Input High Leakage Current Output Low Voltage Output High Voltage High impedance Output Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Xin High Voltage Xin Low Voltage Dynamic Supply Current Power down Supply Current SDATA, SCLK SDATA, SCLK
Condition
Min
3.0 - 2.2 -0.3 2.0
Max
3.6 1.0 - 0.8 3.6 5
Unit
V V V V V A A V V A pF pF nH V V mA mA
Except internal pull up resistors, 0 < VIN < VDD Except internal pull down resistors, 0 < VIN < VDD IOL = 1 mA IOH = -1 mA
-5 - 2.4 -10 2 3 - 0.7VDD 0 0.4 - 10 5 6 7 VDD 0.3VDD 225 60
At max load and freq per Figure 4 Outputs disabled and no power applied to VDD25 and VDD100
- -
AC Electrical Specifications
Parameter
FCLOCK TDC TPERIOD TR / TF TCCJ LLTJ TLOCK VOH VOL
Description
Clock Frequency XIN Duty Cycle
Condition
Min
Typ.
27
Max
Unit
MHz
27M Output Characteristics
The device operates reliably with input duty cycles up to 30/70 but the REF clock duty cycle is not within specification When XIN is driven from an external clock source Measured between 20% and 80% of VOD Measured at 1.5V Measured at 1.5V with 10 s delay Math average Math average 45 - 55 %
XIN Period XIN Rise and Fall Times XIN Cycle to Cycle Jitter Long term Jitter (peak-peak) Clock Stabilization from Power up Voltage High Voltage Low
37.0259 1 -200 -250 - 2.4 -
- - - - - - -
37.0481 3 200 250 2 - 0.4
ns ns ps ps ms V V
100M Output Characteristics FCLOCK TPERIOD TJCC TJLT SPrange SPrate SPprofile Clock frequency Clock period Cycle to Cycle jitter Long Term Jitter (p-p) Spread range Spread rate Spread profile Without spread and without jitter Including +0.0, -0.5% spread and jitter Peak value. Measured at crossing point with spread turned off Measured at crossing point with 10 s delay and spread turned off - 10.000 9.915 -85 -300 -0.5 - - - - - - - 32 Triangular Page 8 of 12 100 - 85 300 0.0 MHz ns ns ps ps % KHz
10.025 10.136
Document #: 001-42225 Rev. *A
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AC Electrical Specifications
Parameter TDC TR/TF TRFM VOX VOX VOH VOL TSKEW TLOCK BWattn Duty Cycle Rise and Fall Times Rise/Fall Matching[1] Description
(continued) Condition Measured at crossing point of the differential signal Measured between 20% and 80% of the VOD Determined as a fraction of 2*(TR-TF)/ (TR+TF) Min 45 175 - 250 - Math average Math average Measured at crossing point VOX Measured at 500 KHz relative to corner frequency 600 -200 - - -20 Typ. - - - - - 710 0.00 - - - Max 55 700 20 550 140 850 50 250 2 - Unit % ps % mV mV mv mv ps ms dB
Crossing Point Voltage at 0.7V Swing Total Variation of VOX over all edges Voltage High[1] Voltage Low
[1]
Output Skew Clock stabilization from power up Closed loop BW attenuation
25M Output Characteristics FCLOCK TCCJ TJLT TDC TR/TF TLOCK VOH VOL FCLOCK TCCJ TJLT TDC TR/TF TLOCK VOH Clock frequency Cycle to Cycle jitter Long Term Jitter (p-p) Duty Cycle Rise and Fall Times Clock stabilization from power up Voltage High Voltage Low Clock frequency Cycle to Cycle jitter Long Term Jitter (p-p) Duty Cycle Rise and Fall Times Clock stabilization from power up Voltage High Math average Math average Peak value Measured at 1.5V with 10 s delay Measured at 1.5V Measured between 20% and 80% of the VOD with 15 pF lumped capacitive load Math average Math average Peak value Measured at 1.5V with 10 s delay Measured at 1.5V Measured between 20% and 80% of the VOD with 15 pF lumped capacitive load - -200 -400 45 1 - 2.4 - - -200 -400 45 0.7 - 2.4 - 25 - - - - - - - 48 - - - - - - - 200 400 55 2 2 - 0.4 200 400 55 3 2 - 0.4 MHz ps ps % ns ms V V MHz ps ps % ns ms V V
48M Output Characteristics
VOL Voltage Low Note 1. Measured at VDD = 3.3V5%
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Test and Measurement Set up
For Single ended Signals
The following diagram shows the test load configurations for the single ended output signals. Figure 3. Single-ended Load Configuration
15pF Lum ped Load
(Including Trace)
For Differential 100 MHz Output Signals
The following diagram shows the test load configuration for the differential CPU and SRC outputs. Trace length is 5 in. Max Figure 4. 0.7V Single-ended Load Configuration
33 49.9
100 Differential
100MT
Measurement Point
5pF (max)
100MC IREF
470
33 49.9
Measurement Point
5pF (max)
Figure 5. Single-ended Output Signals (for AC Parameters Measurement)
TR TF
80% 50% 20% TDC
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Figure 6. Differential Output Signals (for AC Parameters Measurement)
TR, TF
80% VOD, VID VOCM VICM VOL, VIL VOH, VIH
20%
Ordering Information
Part Number Pb free CY28517ZXC CY28517ZXCT 28 pin TSSOP 28 pin TSSOP - Tape and Reel Commercial, 5 to 65C Commercial, 5 to 65C Package Type Product Flow
Package Drawing and Dimensions
Figure 7. 28-Lead Thin Shrunk Small Outline Package (4.40-mm Body) Z28.173
PIN 1 ID
1
DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.16 gms
4.30[0.169] 4.50[0.177]
6.25[0.246] 6.50[0.256]
PART # Z28.173 STANDARD PKG. ZZ28.173 LEAD FREE PKG.
28
0.65[0.025] BSC. 0.19[0.007] 0.30[0.012]
1.10[0.043] MAX.
0.25[0.010] BSC GAUGE PLANE 0-8
0.076[0.003] 0.85[0.033] 0.95[0.037] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008]
9.60[0.378] 9.80[0.386]
51-85120-*A
Document #: 001-42225 Rev. *A
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Document History Page
Document Title: CY28517 PCI Express Clock Generator Document Number: 001-42225 REV. ** *A ECN NO. 1664043 1698623 Issue Date See ECN See ECN Orig. of Change WWZ/AESA New Data Sheet AESA Updated Copyright Description of Change
(c) Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-42225 Rev. *A
Revised November 02, 2007
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All products and company names mentioned in this document may be the trademarks of their respective holders.
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